深圳市硅天下科技有限公司

Hi3521A V100

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編碼器、解碼器 - 集成電路(IC) - 電子元件
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詳細介紹

Key Specifications

Processor Core

ARM Cortex [email protected] 1.1 GHz

Security Engine

AES,DES,and3DESalgorithmsimplementedby hardware

Video Interfaces

multiple protocols

Issue 04 (2016-02-29)

Ethernet Ports

One gigabit Ethernet port

  • ?  RGMII, RMII, and MII modes

  • ?  10/100 Mbit/s half-duplex or full-duplex

  • ?  1000 Mbit/s full-duplex

  • ?  TSO for reducing the CPU usage

    Peripheral Interfaces

    Two SATA 3.0 interfacesPM

    eSATA

    HiSilicon Proprietary and Confidential 3Copyright ? HiSilicon Technologies Co., Ltd

VI interfaces
Four8-bitinterfacesortwo16-bitinterfaces
108MHz/144MHz4xD1/960HTDMinputsforeach8-

bit interface (16xD1/16x960H real-time video inputs in

total)
144 MHz/148.5 MHz 2x720p TDM inputs for each 8-

bit interface ([email protected] fps real-time video inputs in

total)
4x720pTDMinputsthrough148.5MHzdual-edge

sampling or 297 MHz single-edge sampling for each 8- bit interface ([email protected] fps real-time video inputs in total)

148.5MHzBT.1120Y/Cinterleavedmodeforeach8- bit interface ([email protected] fps real-time video inputs in total)

2x1080pTDMinputsthrough148.5MHzdual-edge sampling or 297 MHz single-edge sampling for each 8- bit interface ([email protected] fps real-time video inputs in total)

148.5MHzBT.1120standardmodeforthe16-bit interface ([email protected] fps real-time video inputs in total)

VO interfaces

  • ?  HDMI1.4+VGA+CVBSvideooutputs

  • ?  HDMIandVGAoutputsfromthesamesource

  • ?  [email protected]

  • ?  OneHDgraphicslayerandoneSDgraphicslayerin

    ARGB1555 or ARGB8888 format

  • ?  OnehardwarecursorlayerinARGB1555or

    ARGB8888 format, with the maximum resolution of

    128 x 128

  • ?  Alphablendingofthevideolayer,graphicslayer,and

    cursor layer

Audio Interfaces

Three unidirectional I2S/PCM interfaces

? ?

?

Two input interfaces, supporting 16 multiplexed inputs

One output, supporting dual-channel multiplexed output

16-bit audio inputs and outputs

Hi3521A

Hi3521A H.264 CODEC Processor

page3image42488
page4image480
  •  Two USB 2.0 host ports, supporting the hub

  •  Three UART interfaces, one of which supporting four

    wires

  •  One SPI, supporting two CSs

  •  One IR interface

  •  One I2C interface

  •  Multiple GPIO interfaces

    Memory Interfaces

  •  One 32-bit DDR3/DDR3L SDRAM interface

    • ?  Maximum frequency of 800 MHz

    • ?  ODT

    • ?  Maximum capacity of 1 GB

    • ?  Automatic power consumption control

  •  SPI NOR/NAND flash interface

Configurable Boot Modes

? ? ?

?

?

1-/2-/4-bit SPI NOR/NAND flash
Two CSs, connected to different flash memories Maximum capacity of 32 MB for each CS (only for the

NOR flash)
Maximum capacity of 4 GB for each CS (only for the

SPI NAND flash)
2 KB/4 KB page size (only for the SPI NAND flash) 8-bit/24-bit 1 KB ECC (only for the SPI NAND flash)

?
Embedded 4 KB BOOTROM and 16 KB SRAM

RTC with an Independent Power Supply

Independent battery for supplying power to the RTC

Hi3521ABooting from the SPI NOR flash

Booting from the SPI NAND flashSDK

  •  Linux 3.10-based SDK

  •  Audioencodinganddecodinglibrariescomplyingwith

    various protocols

  •  High-performance H.264 PC decoding library

    Physical Specifications

  •  Power consumption
    Typical power consumption of 3 W
    Multi-level power consumption control

  •  Operatingvoltages
    1.1 V core voltage
    1.25 V CPU voltage
    3.3 V I/O voltage
    1.5 V DDR3 SDRAM interface voltage

  •  Package
    RoHS, TFBGA

    Lead pitch of 0.8 mm (0.03 in.)

    Body size of 19 mm x 19 mm (0.75 in. x 0.75 in.)

  •  Operating temperature ranging from 0°C (32°F) to 70°C

    (158°F)


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聯系方式
深圳市硅天下科技有限公司
固定電話: 13724212401
移動電話: 13724212401
郵箱:
公司地址:華強北群星廣場B座1807室
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聯系人:張生
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